This paper describes a circular first in first out (FIFO) and its protocols which have a very low latency while still maintaining high throughput. Unlike the existing serial FIFOs based on asynchronous micropipelines, this FIFO's cells communicate directly with the input and output ports through a common bus, which effectively eliminates the data movement from the input port to the output port, thereby reducing the latency and the power consumption. Furthermore, the latency does not increase wit...